(1) Field of the Invention
The invention relates to the general field of integrated circuits, more particularly to the formation of copper interconnections therein.
(2) Description of the Prior Art
As wire widths in integrated circuits continue to shrink, the electrical conductivity of the wiring material itself becomes increasingly more important. Thus, in this regard, aluminum, which has been the material of choice since the integrated circuit art began, is becoming less attractive than other better conductors such as copper, gold, and silver. These materials, in addition to their superior electrical conductivity, are also more resistant than aluminum to electromigration, a quality that grows in importance as wire widths decrease.
The metals in question have not been widely used for wiring as yet because they also suffer from a number of disadvantages, including formation of undesirable intermetallic alloys and/or recombination centers in other parts of the integrated circuit and they often have high diffusion rates. Copper has the additional disadvantage of being readily oxidized at relatively low temperatures. Nevertheless, copper is seen as an attractive replacement for aluminum because of its low cost and ease of processing so that the prior and current art has tended to concentrate on finding ways to overcome these limitations.
A particular problem related to copper's high susceptibility to oxidation is that conventional photoresist processing cannot be used when the copper is to be patterned into various wire shapes because the photoresist needs to be removed at the end of the process by heating it in a highly oxidizing environment, such as an oxygen plasma, thereby converting it to an easily removed ash.
Several solutions to the above problems associated with copper processing have been proposed in the prior art. Hoshino (U.S. Pat. No. 4,910,169 March 1990) teaches the use of low temperature deposition techniques, such as RF sputtering, for coating copper layers with materials such as silicon oxide, silicon nitride, and phosphosilicate glass. It should be noted that the materials mentioned were for the purpose of forming inter-metal dielectric layers rather than for use as barrier layers, implying that they were relatively thick.
Li et al. (U.S. Pat. No. 5,447,599 September 1995) use TiN(O) as a barrier layer material for copper. The copper is initially coated with a layer of titanium and a copper-titanium alloy is formed by heating at 3-400° C. Unreacted titanium is then removed and the alloy is transformed to TiN(O) by means of a rapid thermal anneal in ammonia and oxygen.
Nakasaki (U.S. Pat. No. 5,084,412 January 1992) underlays the copper layer with a metallic nitride and then heats the combination in nitrogen to bring about grain boundary diffusion of the nitrogen into the copper. This results in a material having relatively low electrical resistivity together with good resistance to electromigration.
Tokunaga et al. (U.S. Pat. No. 4,931,410 June 1990) use photoresist for shaping their copper but first protect it with an anti-oxidizing layer. Etching is then performed in two steps—first the anti-oxidizing layer is etched in conventional fashion, including photoresist removal, following which said anti-oxidizing layer is used as the mask for the etching of the copper.
Filipiak et al. (U.S. Pat. No. 5,447,887 September 1995) use an intermediate layer of copper silicide to improve the adhesion between a copper layer and a silicon nitride layer.
It should be noted that none of the above-cited examples of the prior art is based on a damascene process. The term ‘damascene’ is derived from a form of inlaid metal jewelery first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar.
Ho et al. (U.S. Pat. No. 5,354,712 October 1994) do teach the use of the damascene process for forming interconnections, including the use of copper together with barrier layers (as discussed above). Ho's teachings are limited to single level metal processes. In particular, Ho et al. do not show (as does the present invention) that, in a double metal process, the barrier layer can also be used as an etch stop layer, thereby simplifying the overall manufacturing process.